The present invention relates, in general, to a semiconductor device manufacturing process, and, in particular, to a method of fabricating a non-silicon-on-insulator (non-SOI) device on a silicon-on-insulator (SOI) starting wafer and thinning the same.
The prior art methods of thinning a semiconductor wafer include a variety of mechanical and chemical means for removing silicon from wafers or dice. Mechanical means for removing silicon include grinding, lapping, polishing, and sputtering. Chemical means for removing silicon include wet chemical etching, dry reactive ion etching, electrochemical methods, and photon assisted electro-chemical methods. In practice, these methods are used in combination. For example, grinding may be performed before lapping. Also, chemical and mechanical polishing, which is the most effective thinning method, may be performed after grinding.
Mechanical grinding is the fastest way to remove material from a semiconductor wafer. It can provide a high degree of uniformity of thickness across a wafer but may also cause damage to the silicon being thinned. Any defect in the crystal structure of a wafer may cause a device fabricated therein to fail.
A chemical etch process may cause poor uniformity of thickness across a wafer. Improved uniformity of thickness may be achieved by including a so-called xe2x80x9cetch stopxe2x80x9d within the device to be thinned by chemical etching. An etch stop is a layer of material which has an etch rate that is much lower than the silicon to be etched. The etch stop serves as an end point to the etch process and is usually made to have a high degree of flatness which in turn results in excellent uniformity of thickness.
The typical etch stop for an SOI wafer (i.e., a buried oxide layer) has some advantages over the typical etch stop for a non-SOI wafer (i.e., a dopant concentration gradient). The buried oxide layer provides an abrupt etch stop and allows for any type of doped silicon layer (i.e., N-type or P-type) to be formed on the oxide layer. An etch stop composed of a buried dopant concentration gradient has a measurable transition length which may increase in size during a subsequent high temperature processing step. Doping has an effect on etch rate. Failure to fabricate an abrupt change in doping concentration provides an ill-defined etch stop which may result in poor uniformity of thickness and unwanted residual dopants. Therefore, an SOI thinning process is superior to a non-SOI thinning process.
A non-SOI fabrication process (e.g., CMOS, NMOS, PMOS, Bipolar, BICMOS, etc.) has some advantages over an SOI fabrication process. For example, a non-SOI wafer is less expensive that an SOI wafer. A non-SOI wafer has, on average, a lower defect density. Non-SOI fabrication lines are more numerous than SOI fabrication lines. Many different circuit technologies (e.g., CMOS, NMOS, PMOS, Bipolar, BICMOS, etc.) may be fabricated in a non-SOI fabrication line than may be fabricated in an SOI fabrication line. The present invention is a method of combining non-SOI fabrication technologies with an SOI thinning process.
U.S. Pat. No. 5,013,681, entitled xe2x80x9cMETHOD OF PRODUCING A THIN SILICON-ON-INSULATOR LAYER,xe2x80x9d discloses a standard SOI thinning process with a novel etch-stop material (i.e., a metal). U.S. Pat. No. 5,013,681 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 5,034,343, entitled xe2x80x9cMANUFACTURING ULTRA-THIN WAFER USING A HANDLE WAFER,xe2x80x9d discloses a method of thinning a wafer, fabricating devices in the thinned wafer, bonding an SOI wafer to the thinned and fabricated wafer, and then thinning this combination. U.S. Pat. No. 5,034,343 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 5,213,986, entitled xe2x80x9cPROCESS FOR MAKING THIN FILM SILICON-ON-INSULATOR WAFERS EMPLOYING WAFER BONDING AND WAFER THINNING,xe2x80x9d discloses a method of implanting ions into a first wafer, growing an oxide on a second wafer, bonding the two wafers together, and thinning the portion containing the ions. U.S. Pat. No. 5,213,986 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 5,234,535, entitled xe2x80x9cMETHOD OF PRODUCING A THIN SILICON-ON-INSULATOR LAYER,xe2x80x9d discloses a method of fabricating a first wafer that includes devices, bonding the first wafer to a second wafer having an oxide layer, and thinning the first wafer. U.S. Pat. No. 5,234,535 is hereby incorporated by reference into the specification of the present invention.
It is an object of the present invention to fabricate a non-SOI device and thin the same using an SO thinning process.
It is another object of the present invention to form a device quality silicon layer on an SOI starting wafer, fabricate a non-SOI device in the SOI wafer, and thin the same using an SOI thinning process.
It is another object of the present invention to provide mechanical support to the thinned device so that the thinned device may be handled and manipulated without being damaged.
The present invention is a method of forming a non-SOI device in an SOI starting wafer and thinning the same using an SOI thinning process. Non-SOI devices include circuity formed in various semiconductor technologies such as NMOS, PMOS, CMOS, Bipolar, BICMOS, and so on. Other devices that may be formed include sensors, mechanical devices, and electromechanical devices. The present invention results in a method that combines the advantages of a non-SOI fabrication process with the superior uniformity of thickness obtained with an SOI wafer thinning process.
The first step in the method is to form a suitable layer of device quality silicon on an SOI starting wafer. The SOI starting wafer consists of a thick, approximately 675 micron (um) thick, silicon substrate covered on one side by a thin, approximately 0.2 um thick, layer of oxide. The device quality silicon layer formed on the SOI starting wafer is approximately 0.2 um thick. To be suitable for the fabrication of non-SOI devices, the device quality silicon layer must be sufficiently thick and appropriately doped to form therein a non-SOI device. This may be accomplished by the epitaxial growth of doped silicon on the device quality silicon layer. Alternatively, instead of forming a silicon layer on the SOI starting wafer, a pre-formed silicon layer may be bonded to an oxide coated silicon wafer to form a xe2x80x9cbondedxe2x80x9d SOI starting wafer.
The second step in the method is to fabricate a non-SOI device in the device quality silicon layer using a non-SOI fabrication process selected by the user.
The third step in the method is to coat the non-SOI device with a layer of polyimide. The polyimide, which is, preferably, 8 um thick, provides mechanical support for the non-SOI device. Any other suitable material may be applied to provide such support. Instead of applying a polyimide layer at this step, it may be applied to the oxide layer of the SOI starting wafer after the silicon substrate of the SOI starting wafer is removed.
The fourth step in the method is to use an SOI thinning process to thin the fabricated wafer. That is, use an SOI thinning process to remove the silicon substrate of the SOI starting wafer so that the user is left with a structure having an oxide layer, a device quality silicon layer on the oxide layer, a device formed in the device quality silicon layer, and a polyimide layer on the device.
The SOI thinning process used by the present method may be as follows. The device resulting from the second step above is bonded device-side down onto a handle wafer. Any suitable bonding material will do, but wax is preferred. Next, the silicon of the SOI starting wafer is coarse ground mechanically. Typically, SOI starting wafers are approximately 675 um thick. Coarse grinding may be used to thin the SOI starting wafer to a thickness within the range of 150 um to 25 um. Next, the SOI starting wafer is chemically etched until the oxide layer of the SOI starting wafer is reached. The oxide layer is commonly referred to as an xe2x80x9cetch stop.xe2x80x9d The last step in the SOI thinning process is to release the thinned device from the handle wafer. If wax is used as the bonding agent, the wax is melted and the thinned device is slid off of the handle wafer.
The present invention combines the best of non-SOI fabrication processes with the superior thinning characteristics of an SOI thinning process. The present method may be used to thin non-SOI devices to below 10 um with uniformity of thickness of better than 5% across a 150 mm device.